1. Field of the Invention
Embodiments of the invention generally relate to the field of semiconductor manufacturing processes, more particularly, to methods for annealing a contact metal layer disposed in contact structures to form a metal silicide layer for semiconductor devices.
2. Description of the Related Art
Integrated circuits may include more than one million micro-electronic field effect transistors (e.g., complementary metal-oxide-semiconductor (CMOS) field effect transistors) that are formed on a substrate (e.g., semiconductor wafer) and cooperate to perform various functions within the circuit. Reliably producing sub-half micron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the limits of integrated circuit technology are pushed, the shrinking dimensions of interconnects in VLSI and ULSI technology have placed additional demands on processing capabilities. Reliable formation of the gate pattern is important to integrated circuits success and to the continued effort to increase circuit density and quality of individual substrates and die.
As feature sizes have become smaller, the demand for higher aspect ratios, defined as the ratio between the depth of the feature and the width of the feature, has steadily increased to 20:1 and even greater. Typically, the contact structure usually includes a silicide, such as nickel silicide (NiSi), cobalt silicide (CoSi2), or titanium silicide (TiSi2) layer. Cobalt silicide and nickel silicide are becoming popular for smaller geometries, e.g., geometries having aspect ratios of about 20:1 or smaller, because CoSi and NiSi are widely available and have lower resistivity and lower contact resistance compared to other metal silicides.
In a typical fabrication process, a pre-clean process is performed before the metal silicide is formed on a substrate in one vacuum environment. Subsequently, a contact metal layer is deposited on the substrate using a physical vapor deposition process followed by a thermal process to perform a metal silicidation process. During the thermal processing process, the heat energy provided during the metal silicidation process may assist crystallization of the metal silicide layer, thereby affecting the overall electrical performance, such as working function shift, of the semiconductor devices. Furthermore, poor crystallinity of the metal silicide layer may also result in undesired high contact resistance, thereby resulting in poor electrical properties of the device characteristics. In addition, poor nucleation resulted from inappropriate thermal energy processing during the metal silicidation process may further result in different stoichiometric ratios of metal elements to silicon elements formed in the resultant metal silicide layer, which may impact not only on the electrical performance of the devices, but also on the integration of the deposition of the conductive contact material subsequently formed thereon.
Therefore, there is a need for an improved method for annealing a contact metal layer to fabricate a metal silicide fabrication process.